New communication and navigation systems are demanding radio frequency (RF), micro- and millimeter-wave power amplifiers which are similar in operation to high performance digital-to-analog converters (DACs). These power amplifiers (PAs) must be capable of producing high power over wide frequency ranges with high direct current (DC)-to-RF efficiency, linear amplitude control over several decades and with minimum size/weight. Many of these systems must also generate linear waveforms with tight spectral control and also supply complete digital control of all the PA and DAC functions for software controlled applications.
Currently employed linearization techniques such as pre-distortion, feed-forward, and envelope restoration are limited in bandwidth, temperature range, and efficiency.
Achieving high powers have required DAC designers to use high speed devices such as, bipolar transistors, HEMTs, IGBTs or MOSFETs with large active areas (in terms of total gate width or emitter area) to obtain the specified power levels. As the device size increases however, a limit is reached in how large a device can be electrically, and how low its terminal impedances can be in terms of the ability of matching circuits to reach the extremely low impedances on the input and output of the device. Matching to large devices requires large transformation ratios which are inherently frequency band limited. This may be compounded in multi-stage power amplifiers where bandwidth limitations become even more severe as more gain stages are cascaded.
Nonlinear operation of the power amplifier is required to yield the highest efficiency, with switched mode operation being a commonly employed technique. This mode of operation can be employed with square wave drive excitation, fast rise and fall times, and push-pull differential phasing, with minimal dead time between the positive and negative rail drive excitation.
The primary function of a DAC is to convert a low power digital signal to an equivalent analog signal in a fast, efficient and precise manner. Different architectures have been used in the past to create high-speed, low-distortion DACs. DAC circuit topologies currently in use in the industry include pulse width modulator, oversampling (Delta-Sigma), R-2R, binary-weighted resistor and current-scaled DACs. In a pulse width modulator DAC a stable current or voltage is switched into a low-pass analog filter. The oversampling technique allows for the use of a lower resolution, typically 1-bit, DAC internally. R-2R DAC's have variable source impedance depending upon which resistor ladders are switched into the circuit. Weighted resistor DAC's have binary weighted resistors which directly scale the analog output voltage. In both topologies, the output voltage is less than the input voltage.
Many high speed DACs make use of some form of non-saturating current-mode switching. A straight binary DAC with one current switch per bit produces code-dependent glitches and is certainly not the most optimum architecture. A DAC with one current source per code level can be shown not to have code-dependent glitches, but it is not practical to implement for high resolutions. Current-Scaled DAC's simply scale binary weighted constant current sources or sinks based on the digital input. All of the above examples are implemented at a low power level where the main concern is the conversion of the signal. If a high-power analog signal is needed, another amplifier stage must be cascaded to provide the needed voltage or current drive.
Also almost all of the above examples have either pull up or pull down semiconductor devices (but not both), so either the rise or fall time for a voltage transition can be very slow.
Thus, a power amplifier architecture yielding linear or pseudo linear operation while maintaining system efficiency is desirable.